1. Technical Field
The present invention relates to a test apparatus. In particular, the present invention relates to a test apparatus that recovers a clock signal from an output signal of a device under test.
2. Related Art
A test apparatus that tests a device under test including a high-speed serial interface that buries a clock signal is known, as in, for example, Patent Documents 1 and 2. Each of these test apparatuses uses a PLL to recover a clock signal from an output signal of a device under test, and acquires the logic value of the output signal with a timing comparator at a timing based on the recovered clock signal.
Patent Document 1: Japanese Patent Application Publication No. 2005-285160
Patent Document 2: Japanese Patent Application Publication No. 2007-017257
The path on which the output signal and the clock signal are transmitted changes the signal delay time according to the frequency and level of the output signal and the clock signal. Therefore, when the type of device under test is changed, the level and frequency of the output signal change as well, which causes a phase difference between the clock signal and the output signal input to the timing comparator.
When there is a phase difference between the output signal and the clock signal, the timing at which the timing comparator acquires the output signal changes. When the acquisition timing of the output signal changes, an error arises in the acquired results. Accordingly, when the frequency and the level of the output signal change, the test apparatus cannot perform accurate testing.